Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■PCMC (PCI, Cache & Memory Controller)
Vendor ID 8086h (Intel)
Device ID 04A3h
Base class 06h (Bridge device)
Subclass 00h (PCI-HOST CPU bridge)
Terminology PCI configuration register
o Used to set various settings for the 82434 (PCMC).
o When configuration mechanism #1 is selected, the PCI configuration register
is mapped to I/O C000-CFFFh in the CPU's I/O space.
Related I/O 0CF8h
I/O 0CF9h
I/O 0CFAh
I/O C000-CFFFh
I/O 0CF8h,0CFCh
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PCI 00h,01h
Name Vendor ID (VID)
Undocumented
Function
[READ]
Bit 15-0: Vendor ID (VID)
* Intel's vendor ID is 8086h.
Explanation o Returns the PCMC vendor ID. This register is read-only.
PCI 02h,03h
Name Device ID (DID)
Undocumented
Function
[READ]
Bit 15-0: Device ID (DID)
* Intel's PCMC (82434LX/NX) device ID is 04A3h.
Explanation o Returns the 82434 (PCMC) device ID. This register is read-only.
PCI 04h,05h
Name Command Register (PCICMD)
Undocumented
Function
[READ/WRITE]
Bit 15-9: Reserved
Bit 8: SERR# Enable (SERRE)
1 = Enabled
0 = Disenabled
bit 7: Reserved
bit 6: Parity Error Enable (PERRE)
1 = Support parity checking on PCI
0 = No Parity checking on PCI
bit 5-3: Reserved
bit 2: Bus Master Enable (BME)
1 = Enabled
0 = Disenabled
* This bit is read-only.
Always enabled.
bit 1: Memory Access Enable (MAE)
1 = Enabled
0 = Disenabled
bit 0: I/O Access Enable (IOAE)
1 = Enabled
0 = Disenabled
* This bit is read-only.
Always disabled.
Description o Sets the basic capabilities of the PCMC.
PCI 06h,07h
Name Status Register (PCISTS)
Undocumented
Function
[READ/WRITE]
bit 15: Reserved
bit 14: System Error Propagation (SSE)
1 = SERR# asserted by PCMC
0 = SERR# not asserted by PCMC
bit 13: Master Abort Receive Status (RMAS)
1 = Master abort
0 = No master abort
bit 12: Target Abort Receive Status (RTAS)
1 = Target abort
0 = No target abort
bit 11: Reserved
bit 10,9: DEVSEL# Timing (DEVT)
* This bit is read-only. Always 10b.
bit 8: Data Parity Detect (DPD)
1 = PCI Data Parity Error Detected
0 = No PCI Data Parity Error Detected
bit 7-0: Reserved
Description o Reads the status of PCI bus errors, etc.
PCI 08h
Name Revision ID (RID)
Undocumented
Function
[READ]
Bits 7-0: Revision ID (RID)
03h = 82434LX A-3 stepping
10h = 82434NX A-0 stepping
11h = 82434NX A-1 stepping
* Returns the revision ID of the PCMC.
Description o Returns the revision ID of the 82434 (PCMC). This register is read-only.
u The 82434NX PCMC installed in the PC-9821Xt and Xa is distributed in a
mixture of A-0 step with revision ID 10h and A-1 step with revision ID 11h.
Posting to memory cannot be used with the 82434NX A-0 step.
PCI 09h
Name Register Level Programming Interface (RLPI)
Undocumented
Function
[READ]
Bits 7-0: Register Level Programming Interface (RLPI)
* PCMC returns 00h.
Description o Indicates that PCMC does not have a register level programming interface.
This register is read-only.
PCI 0Ah
Name Subclass Code (SCCD)
Undocumented
Function
[READ]
Bits 7-0: Subclass Code (SCCD)
* PCMC returns 00h.
Description o Indicates that PCMC is a bridge device between the host CPU and the PCI bus.
This register is read-only.
PCI 0Bh
Name Base Class Code (BCCD)
Undocumented
Function
[READ]
Bits 7-0: Base Class Code (BCCD)
* Initial value 06h
Description o Indicates that PCMC is a bridge device.
This register is read-only.
PCI 0Dh
Name Master Latency Timer (MLT)
Undocumented
Function
[READ/WRITE]
bit 7-4: Master Latency Timer Count Value
bit 3-0: Reserved
Explanation o Sets the PCI bus occupation time for PCMC.
PCI 0Fh
Name BIST Register (BIST)
Undocumented
Function
[READ]
bit 7: BIST Support
bit 6: BIST Start
bit 5,4: Reserved
bit 3-0: Completion Code
Explanation o 82434LX/NX does not support BIST (Bulid In Self Test), so 00h is always read.
PCI 50h
Name Host CPU Selection (HCS)
Undocumented
Function
[READ/WRITE]
bit 7-5: Host CPU Type (HCT)
100b = Pentium Processor 60MHz/66MHz (P5)■[82434LX]
101b = Pentium Processor 90MHz/100MHz (P54C)■[82434NX]
* These 3 bits are read-only.
bit 4,3: Reserved
bit 2: First level cache enable (FLCE)
1 = Enabled
0 = Disenabled
bit 1,0: Host operating frequency (HOF)
■[82434LX]
00b = 60MHz
01b = 66MHz
10b = Undefined
11b = Undefined
■[82434NX]
00b = 50MHz
01b = Reserved
10b = 60MHz
11b = 66MHz
Description o Selects the host CPU.
o The DRAM refresh rate is adjusted by the value of bits 1,0.
PCI 51h
Name De-Turbo Frequency Control (DFC)
Undocumented
Function
[READ/WRITE]
bit 7,6: De-Turbo mode frequency adjustment value
00b = Reserved
01b = Low
10b = Medium
11b = High
bit 5-0: Reserved
Description o Sets the percentage at which AHOLD is asserted when the CPU is put into a wait state using the CPU's AHOLD pin.
PCI 52h
Name Secondary Cache Control (SCC)
Undocumented
Function
[READ/WRITE]
bit 7,6: Secondary Cache Size (SCS)
00b = No cache implemented
01b = Reserved
10b = 256KB
11b = 512KB
bit 5: SRAM Type (SRAMT)
1 = Burst SRAM
0 = Standard SRAM
bit 4: Secondary Cache Allocation (SCA)
1 = CACHE# Active or Inactive
0 = CACHE# Active
bit 3: Cache Byte Control (CBC)
1 = Byte Write Enable
0 = Byte Select
bit 2: SRAM Connection (SRAMC) ■ [82434NX]
bit 1: Secondary Cache Write Policy (SCWP) ■ [82434LX]
1 = Write Back
0 = Write Through
bit 0: Secondary cache enable (SCE)
1 = Secondary cache enabled
0 = Secondary cache disabled
Explanation o Sets the secondary cache.
o In the 82434NX, the secondary cache always performs write-back operations.
PCI 53h
Name Host Read/Write Buffer Control (HBC)
Undocumented
Function
[READ/WRITE]
Bits 7-4: Reserved
Bit 3: Read-around-write enable (RAWCM)
1 = Enabled
0 = Disenabled
Bit 2: Reserved
Bit 1: Enable posting from host to PCI (HPPE)
1 = Enabled
0 = Disenabled
Bit 0: Enable posting from host to memory (HMPE)
■[82434LX]
1 = Enabled
0 = Disenabled
■[82434NX A-0 step]
1 = Prohibited
0 = Disenabled (always set to 0)
■[82434NX A-1 step and later]
1 = Enable
0 = Enable
Explanation o Sets whether to enable the write buffer in the 82433 (LBX).
From the A-1 step of the 82434NX onwards, posting from the host to memory is
always enabled regardless of the setting of bit 0, and write data from the
host to main memory within LBX posting is posted. However, in the A-0 step of
the 82434NX, posting from the host to memory cannot be used, so bit 0 must be
set to 0. For the PC-9821Xt and Xa, a mixture of the A-0 and A-1 steps of the
82434NX are distributed, so it is necessary to refer to the revision ID and
set it appropriately.
PCI 54h
Name PCI Read/Write Buffer Control (PBC)
Undocumented
Function
[READ/WRITE]
Bits 7-3: Reserved
Bit 2: LBX connection to TRDY#
1 = LBXs are connected to TRDY#
0 = LBXs are not connected to TRDY#
Bit 1: PCI Burst Write Enable (PBWE)
1 = Enabled
0 = Disenabled
Bit 0: PCI to Memory Posting Enable (PMPE)
■[82434LX, 82434NX A-1 step and later]
1 = Enabled
0 = Disenabled
■[82434NX A-0 step]
1 = Setting prohibited
0 = Disenabled (always set to 0)
Explanation o Enables/disables PCI to Memory transfers.
o Sets whether to aggregate single CPU to PCI transfers into PCI burst cycles.
In the A-0 step of the 82434NX, posting of write cycles from PCI to memory is
not possible, so bit 0 must be set to 0. For the PC-9821Xt and Xa, the A-0 and
A-1 steps of the 82434NX are mixed, so it is necessary to refer to the
revision ID and set it appropriately.
PCI 55h
Name Secondary cache control extension register (SCCE)
Undocumented
Target Models with 82434NX
Function
[READ/WRITE]
bit 7-1: Reserved
bit 0: Zero wait state (ZWS)
----+------------+------------+-------------
ZWS | | Burst SRAM | Standard SRAM
----+------------+------------+-------------
1 | Read hit | 2-1-1-1 | 2-2-2-2
| Write hit | 2-1-1-1 | 3-2-2-2
----+------------+------------+-------------
0 | Read hit | 3-1-1-1 | 3-2-2-2
| Write hit | 3-1-1-1 | 4-2-2-2
----+------------+------------+-------------
* When the CPU clock is 60MHz or 66MHz, set this to 0.
Explanation o Sets the number of wait states when transferring the first data
of a secondary cache hit.
PCI 57h
Name DRAM Control
Undocumented
Function
[READ/WRITE]
bit 7,6: DRAM burst timing (DBT) ■ [82434NX]
00b = X-4-4-4 read/write
01b = X-4-4-4 read, X-3-3-3 write
10b = Reserved
11b = X-3-3-3 read/write
bit 5: Parity error mask (PERRM)
1 = Enabled
0 = Disenabled
bit 4: 0-Active RAS# Mode
1 = 0-Active RAS# Mode
0 = 1-Active RAS# Mode
bit 3: SMRAM enable (SMRE)
1 = Enabled
0 = Disenabled
bit 2: 4 refresh burst (BFR)
1 = Burst of four refresh
0 = Single refresh
bit 1: Refresh type (RT)
1 = CAS# Before RAS# refresh
0 = RAS# only refresh
bit 0: Refresh enable (RE)
1 = Enabled
0 = Disenabled
Description o Sets the DRAM controller.
PCI 58h
Name DRAM Timing (DT)
Undocumented
Function
[READ/WRITE]
bit 7-2: Reserved
bit 1: RAS#wait state (RWS)■[82434NX]
1 = 1 wait
0 = 0 wait
* 0 is set on PC-9821Xt and Xa.
bit 0: CAS#wait state (CWS)
1 = 1 wait
0 = 0 wait
* 0 is set on PC-9821Xt and Xa.
Explanation o Sets whether to add a wait to the CPU when the CPU accesses the DRAM.
PCI 59-5Fh
Name Programmable Attribute Map (PAM)
Undocumented
Function
[READ/WRITE]
bit 7: R(Reserved)
* Reserved
bit 6: CE(CacheEnable)
1 = Cacheable
0 = Not cacheable
bit 5: WE(WriteEnable)
1 = Writeable
0 = Not writeable
bit 4: RE(ReadEnable)
1 = Readable
0 = Not readable
bit 3-0: R,CE,WE,RE
* Same as bits 7-4
The memory ranges set by each register are as follows.
---------+-----+-------------------------------
Register | Bit | Memory range
---------+-----+-------------------------------
59h | 3-0 | 080000-09FFFFh (Memory window)
59h | 7-4 | 0F0000-0FFFFFh (BIOS area)
5Ah | 3-0 | 0C0000-0C3FFFh (Extended ROM area)
5Ah | 7-4 | 0C4000-0C7FFFh (Extended ROM area)
5Bh | 3-0 | 0C8000-0CBFFFh (Extended ROM area)
5Bh | 7-4 | 0CC000-0CFFFFh (Extended ROM area)
5Ch | 3-0 | 0D0000-0D3FFFh (Extended ROM area)
5Ch | 7-4 | 0D4000-0D7FFFh (Extended ROM area)
5Dh | 3-0 | 0D8000-0DBFFFh (Extended ROM area)
5Dh | 7-4 | 0DC000-0DFFFFh (Extended ROM area)
5Eh | 3-0 | 0E0000-0E3FFFh (VRAM area)
5Eh | 7-4 | 0E4000-0E7FFFh (VRAM area)
5Fh | 3-0 | 0E8000-0EBFFFh (BIOS area)
5Fh | 7-4 | 0EC000-0EFFFFh (BIOS area)
---------+-----+-------------------------------
The combinations to be set for bits 7-4 or bits 3-0 are as follows.
----------------+--------------------------------------------------
bit 7-4 or |
bit 3-0 value | operation
----------------+--------------------------------------------------
xx00b | DRAM disabled, direct access to PCI bus
x001b | Read only, DRAM write protect, cache prohibited
x101b | Read only, DRAM write protect, cache allowed
x010b | Write only
x011b | Read/write allowed, cache prohibited
x111b | Read/write allowed, cache allowed
----------------+--------------------------------------------------
Explanation o Sets the memory access behavior for the specific memory area set in each register.
u On the PC-9821X-B02 SCSI-2 interface board, this configuration register of
PCMC is manipulated to set the PCI EXTENDED MEMORY where the SCSI BIOS is
located to be read/write enabled. This is because the SCSI BIOS uses it as a work area.
PCI 60-65h■[82434LX]
PCI 60-67h■[82434NX]
Name DRAM Row Boundary Register (DRB)
Undocumented
Function
[READ/WRITE]
bit 7-0: Row Boundary Address in MBytes
Name and setting of each register
---------+------+----------------------------------------
Register | Name | Setting value
---------+------+----------------------------------------
60h | DRB0 | Memory capacity of ROW#0 (MB)
61h | DRB1 | Total memory capacity of ROW#0,#1 (MB)
62h | DRB2 | Total memory capacity of ROW#0-2 (MB)
63h | DRB3 | Total memory capacity of ROW#0-3 (MB)
64h | DRB4 | Total memory capacity of ROW#0-4 (MB)
65h | DRB5 | Total memory capacity of ROW#0-5 (MB)
66h | DRB6 | Total memory capacity of ROW#0-6 (MB)■[82434NX only]
67h | DRB7 | Total memory capacity of ROW#0-7 (MB)■[82434NX only]
---------+------+----------------------------------------
Figure: Correspondence between SIMM sockets and row boundaries
--------+-----------------------+---------------
RAS | Socket (Side) | Register
--------+-----------------------+---------------
RAS#7 | #7(Back), #6(Back) | DRB7■[82434NX only]
RAS#6 | #7(Front),#6(Front) | DRB6■[82434NX only]
--------+-----------------------+---------------
RAS#5 | #5(Back), #4(Back) | DRB5
RAS#4 | #5(Front),#4(Front) | DRB4
--------+-----------------------+---------------
RAS#3 | #3(Back), #2(Back) | DRB3
RAS#2 | #3(Front),#2(Front) | DRB2
--------+-----------------------+---------------
RAS#1 | #1(Back), #0(Back) | DRB1
RAS#0 | #1(Front),#0(Front) | DRB0
--------+-----------------------+---------------
* 72-pin SIMMs are 32-bit wide, so to make it 64-bit wide, SIMMs must be
installed in even numbers.
* For 4MB and 16MB SIMMs, only the even-numbered RAS is used. In this case,
set DRBn+1 to the same value as DRBn.
Explanation o The 82434LX controls six DRAM row addresses, and the 82434NX controls eight.
o This register sets the address for each memory installed in the SIMM socket.
o One physical SIMM socket consists of two logical SIMM sockets, and 2MB, 8MB,
and 32MB SIMMs can be used.
PCI 68-6Bh■[82434NX]
Name DRAM Row Boundary Extension Register (DRB)
Undocumented
Function
[READ/WRITE]
bit 31-28: DRB7 Extention
bit 27-24: DRB6 Extention
bit 23-20: DRB5 Extention
bit 19-16: DRB4 Extention
bit 15-12: DRB3 Extention
bit 11-8: DRB2 Extention
bit 7-4: DRB1 Extention
bit 3-0: DRB0 Extention
Explanation o Controls the eight DRAM row addresses extended by the 82434NX.
PCI 70h
Name Error Command (ERRCMD)
Undocumented
Function
[READ/WRITE]
bit 7: Target Abort Receive SERR#
bit 6: PCI Data Parity Error Send SERR#
bit 5: PCI Data Parity Error Receive SERR#
bit 4: PCI Address Parity Error SERR#
bit 3: Data Parity Error Receive PERR#
1 = Enabled
0 = Disenabled
bit 2: L2 Cache Parity Enable
1 = L2 cache implements parity
0 = L2 cache does not implement parity
bit 1: DRAM/L2 Cache Data Parity Error SERR# Enable
bit 0: DRAM/L2 Cache Data Parity MCHK Enable
1 = Enabled
0 = Disenabled
Description o Sets how PCMC handles various system errors.
PCI 71h
Name Error Status (ERRSTS)
Undocumented
Function
[READ/WRITE]
bit 7: Reserved
bit 6: PCI transmit data parity error
1 = Data Parity Error
0 = No Data Parity Error
bit 5: PCI receive data parity error ■ [82434NX]
1 = Data Parity Error
0 = No Data Parity Error
bit 4: PCI address parity error ■ [82434NX]
1 = Data Parity Error
0 = No Data Parity Error
bit 3: Main memory data parity error
1 = DRAM Data Parity Error
0 = No DRAM Data Parity Error
bit 2: L2 cache data parity error
1 = L2 Cache Data Paritye Error
0 = No L2 Cache Data Paritye Error
bit 1: Reserved
bit 0: Shutdown cycle detection
1 = Shutdown Cycle
0 = No Shutdown Cycle
Explanation o Indicates PCI, L2 cache, or DRAM parity errors.
o Writing a 1 to each bit clears the error indication.
PCI 72h
Name SMRAM Space Control (SMRS)
Undocumented
Function
[READ/WRITE]
bit 7,6: Reserved
bit 5: SMRAM Space Open (OSS)
1 = SMRAM Access Open
0 = SMRAM Access in SMM only
bit 4: SMRAM Space Close (CSS)
1 = Data Access to PCI
0 = Data Access to SMRAM
bit 3: SMRAM Space Lock (LSS)
1 = SMRAM Locked
0 = SMRAM Not Locked
bit 2-0: SMM Base Segment (SBS)
000b = Top of main memory
001b = Reserved
010b = A0000-AFFFFh
011b = B0000-BFFFFh
100b = Reserved
101b = Reserved
110b = Reserved
111b = Reserved
Explanation o Sets the memory space in which SMRAM is allocated.
PCI 78h,79h
Name Memory Space Gap (MSG)
Undocumented
Function
[READ/WRITE]
bit 15: Memory Space Gap Enable
1 = Enabled
0 = Disenabled
bit 14-12: Memory Space Gap Size
000b = 1MB
001b = 2MB
011b = 4MB
111b = 8MB
*Other combinations are reserved.
*Fixed to 0000b (1MB) on PC-9800 series
bit 11-8: Reserved
bit 7-4: Memory Space Gap Starting Address
MSGSA = A[23:20]
*Fixed to 1111b (F00000h and above) on PC-9800 series
bit 3-0: Reserved
Explanation o Sets the non-contiguous memory area in the CPU address space.
o In the PC-9800 series, it is used to set the 16MB system space.
Related I/O 043Bh bit 2
PCI 7C-7Fh
Name Frame buffer area (FBR)
Undocumented
Function
[READ/WRITE]
bit 31-20: Buffer offset
* Sets bits 31-20 of the offset address of the frame buffer.
bit 19-14: Reserved
bit 13: Byte merging
1 = Enabled
0 = Disenabled
bit 12: 128K VGA region attribute enable
1 = Enabled
0 = Disenabled
bit 11,10: Reserved
bit 9: No lock request
1 = No LOCK Request enabled
0 = No LOCK Request disenabled
bit 8: Prefetch from CPU to PCI
1 = Prefetch enabled
0 = Prefetch disenabled
bit 7: Transparent buffer write
1 = Flush not required
0 = Flush required
bit 6-4: Reserved
bit 3-0: Buffer region
0000b = 1MB
0001b = 2MB
0011b = 4MB
0111b = 8MB
1111b = 16MB
Description o Defines the memory region for the frame buffer.
-------------------------------------------------------------------------------